The present invention relates to redundant signed digit (RSD) analog-to-digital converters and more particularly to a low power single stage RSD A/D converter.
Advances in integrated circuit technology have enabled the development of complex xe2x80x9csystem-on-a-chipxe2x80x9d ICs for a variety of applications such as wireless communications and digital cameras. Such applications are embodied in portable electronic devices for which low power and small circuit area are key design factors. Low power and low voltage circuits are needed to decrease battery power requirements, which can allow for designs requiring fewer or smaller batteries, which in turn decreases device size, weight and operating temperature.
Such devices, however, receive analog input signals that must be converted to digital signals. Various conventional cyclic (algorithmic) A/D converters that achieve low power operation and high resolution in a small area are known. For example, U.S. Pat. No. 5,644,313, herein incorporated by reference, assigned to Motorola Inc., the assignee of the present invention, discloses a cyclic RSD having two RSD stages followed by a digital logic section that performs synchronization and correction functions.
Referring to FIG. 1, a block diagram of a cyclic RSD A/D converter 10, such as the one disclosed in U.S. Pat. No. 5,644,313, is shown. The A/D converter 10 includes an analog section having two RSD stages 11 and 12 followed by digital section 14 having an alignment and synchronization block 15 and a correction block 16. An analog input signal (voltage) is input to the first RSD stage 11 by way of a switch 18. After the input signal is received, the switch 18 is opened. The first RSD stage 11 compares the input signal to a high voltage (VH) and a low voltage (VL) and generates a first digital output signal, in this case the msb, based on the comparison results. The first RSD stage 11 also generates a first residue voltage VR1. The msb is output to the digital section 14 and the residue voltage VR1 is input to the second RSD stage 12. The second RSD stage 12 also performs high and low voltage comparison operations, generates a second digital output signal (msb-1), and a second residue voltage VR2. The second digital output signal (msb-1) is output to the digital section 14, the switch 18 is moved to connect the feedback path, and the second residue voltage VR2 is provided to the first RSD stage 11. This operation is repeated, with the RSD stages 11, 12 outputting additional digital bits of the input signal. The digital bits are aligned, synchronized, and combined in the digital section 14 to provide a standard format binary output code.
While this two-stage solution provides a low power, high resolution and high speed A/D converter, there is a need for an A/D converter having minimal power requirements, equivalent speed and decreased silicon area.
In order to provide a low power, high speed, high resolution A/D converter that does not take up a lot of space, the present invention provides a cyclic A/D converter in which a single stage is used repeatedly to perform the conversion. Low power consumption is achieved through the use of an efficient gain/addition/subtraction block that performs the same functions at the same speed as the aforementioned two-stage cyclic ADC but with approximately half the circuitry. The single stage has a directly connected feedback loop that provides a residual voltage output signal to the single stage input terminal.